As is well known by those skilled in the art, a continuing goal in the manufacture and production of semiconductors is a reduction in the size of components and circuits with the concurrent result of an increase in the number of circuits and/or circuit elements, such as transistors, capacitors, etc., on a single semiconductor device. This relentless and successful reduction in size of the circuit elements has also required reduction in the size of the conductive lines connecting devices and circuits.
In the past, aluminum was used for metal interconnect lines and silicon oxide was used for the dielectric. However, newer manufacturing techniques now favor copper as the metal for forming interconnect lines and various low K materials (organic and inorganic) for forming the dielectric material. Not surprisingly, these material changes have required changes in the processing methods. In particular, because of the difficulty of etching copper without also causing unacceptable damage to the copper and/or dielectric material, the technique of forming the metal interconnect lines has experienced significant changes. Namely, whereas aluminum interconnects could be formed by depositing a layer of aluminum and then using photoresist, lithography, and etching to leave a desired pattern of aluminum lines, copper interconnect lines are typically formed by a process now commonly referred to as a damascene process. The damascene process is almost the reverse of etching. Simply stated, a trench, canal or via is cut, etched or otherwise formed in the underlying dielectric and is then filled with metal (i.e., copper).
The damascene process has allowed even further reductions in the size of interconnect lines and the space between the interconnect lines. Unfortunately, as the space between the interconnecting lines has decreased, the line-to-line capacitance has increased.
As stated above, the change in materials and processing steps has resulted in a new set of manufacturing challenges. For example, the patterning and etching of the dielectric layer that supports and surrounds a via interconnecting an upper or second metallization layer to a lower metallization level, and then the removal of the resist or hard mask by the typical “ashing” process often results in considerable damage to the top surface of the copper of the lower metallization level at the point of the interconnection. This damage may result in decreased yields, and, therefore, etching techniques and the method of removal of the resist need some adjustments.